1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device permitting reduction of time required for testing.
2. Description of the Background Art
As the integration density of semiconductor devices increases, increase in time required for testing to validate operation came to be a significant problem. In particular, some semiconductor memory devices have a so-called multi-bit test mode as a measure to solve the problem, according to which data is written into a plurality of memory cells at a time, and data is read out from the plurality of memory cells written with the data.
FIG. 16 is a schematic diagram of the configuration of a main part of a conventional semiconductor memory device.
Referring to FIG. 16, the conventional semiconductor memory device includes a column main decoder 642 which receives internal address signals CAD[0], /CAD[0], CAD[1], /CAD[1], CAD[2], and /CAD[2], and activates one of column selecting lines CSL0 to CSL7, and row main decoders 650 and 652 which receive internal address signals RAD[0] to RAD[3], /RAD[0] to /RAD[3] generated in response to externally applied row address signals RA0 to RA3, and activates one of 16 word lines WL0 to WL15.
The conventional semiconductor memory device further includes a memory cell array 644 having memory cells arranged in a matrix and activated by word lines WL0 to WL7, and a memory cell array 648 having memory cells arranged in a matrix and activated by word lines WL8 to WL15.
The conventional semiconductor memory device further includes an I/O gate-sense amplifier portion 646 for amplifying data in corresponding memory cells in the memory array in response to activation of word lines WL0 to WL15, and connecting corresponding bit lines to I/O lines IOA, /IOA, IOB, and /IOB in response to activation of column selecting lines CSL0 to CSL7, a differential amplifier 680 having its plus and minus input nodes connected to I/O lines IOA and /IOA, respectively, a differential amplifier 678 having its plus and minus input nodes connected to I/O lines IOB and /IOB, respectively and an EXNOR circuit 682 which receives the outputs of differential amplifiers 678 and 680.
The conventional semiconductor memory device further includes I/O line isolation gates 668 and 666 activated by internal address signal CAD[3] to electrically connect I/O lines IOA and /IOA and I/O lines IO and /IO, respectively, I/O line isolation gates 664 and 662 activated by internal address signal /CAD[3] to electrically connect I/O lines IOB and /IOB and I/O lines IO and /IO, respectively, a differential amplifier 670 having its plus and minus input nodes connected to I/O lines IO and /IO, respectively, a buffer 676 for outputting a data output signal to an output terminal Dout, an output line isolation gate 684 activated by a test mode signal TE to electrically connect the output node of EXNOR circuit 682 and the input node of buffer 676, an inverter 674 for inverting received test mode signal TE, and an output line isolation gate 672 activated by the output signal of inverter 674 to electrically connect the output node of differential amplifier 670 and the input node of buffer 676.
The conventional semiconductor memory device further includes an inverter 654 which receives and inverts a signal externally applied to an input terminal Din, an inverter 656 which receives and inverts a writing control signal WDE generated in response to an externally applied writing signal, a clocked inverter 658 activated by writing control signal WDE to invert a signal applied to input terminal Din, and output the resulting signal to I/O line /IO, and a clocked inverter 660 activated by writing control signal WDE to invert the output signal of inverter 654 and output the resulting signal to I/O line 10.
The semiconductor memory device selects one of 256 memory cells by signals of 8 bits in total, i.e., address signals RA0 to RA3, and CA0 to CA3, writes data input from input terminal Din to a memory cell in a writing cycle, and outputs data held in a selected memory cell to output terminal Dout in a reading cycle.
In a normal operation mode, 256 cycles are necessary for each of writing and reading, in order to test the operation of the semiconductor memory device.
The semiconductor memory device has a test mode which halves time required for testing, by performing writing/reading on a two-memory-cell basis, in order to increase the operation test speed.
Referring to FIG. 16, in the test mode, test mode signal TE is at an H (High) level, internal address signals CAD3 and /CAD3 are both activated regardless of an input address.
As a result, in a writing cycle in the test mode, data input from input terminal Din is transmitted to I/O lines IOA, /IOA, IOB, and /IOB through I/O line isolation gates 662, 664, 666 and 668.
One of column selecting lines CSL0 to CSL7 is activated by column main decoder 642 in response to internal address signals CAD[0] to CAD[2], and /CAD[0] to /CAD[2] generated based on column addresses CA0 to CA2.
Data on an I/O line is transmitted to two bit line pairs through an I/O gate selected in IO gate-sense amplifier 646 by the activated column selecting line, and the same data is written into two memory cells selected by row main decoder 650 or 652 by internal address signals RAD[0] to RAD[3], and /RAD[0] to /RAD[3] generated based on a row address.
In a reading cycle in the test mode, data in two memory cells written with the same data in a writing cycle in the test mode is read out by selecting word lines WL0 to WL15, column selecting lines CSL0 to CSL7, similarly to the case of writing, but in the opposite path from I/O lines IOA, /IOA, IOB to /IOB.
Two pieces of data read out on I/O lines IOA, /IOA, IOB and /IOB are amplified by differential amplifiers 680 and 678. If the semiconductor memory device is operating normally, the outputs of differential amplifiers 680 and 678 provided by amplifying data read out from the memory cells written with the same data are in coincidence, and the output of EXNOR circuit 682 attains an H (high) level. The output of EXNOR circuit 682 is selected by test mode signal TE and connected to the input node of output buffer 674, and therefore an H level is output to output terminal Dout.
If the semiconductor memory device is not operating normally, and different data is output to differential amplifiers 680 and 678, an L (low) level is output to output terminal Dout.
As a result, in the test mode, an operation test may be performed on a 2-bit basis, and time required for testing may be halved.
FIG. 17 is a circuit diagram of a conventional semiconductor memory device disclosed by U.S. Pat. No. 5,021,998.
The circuit diagram shows in further detail memory cell arrays 644 and 648, and I/O gate-sense amplifier 646 shown in FIG. 16.
Referring to FIG. 17, a memory cell array 644 includes a capacitor 724 which stores data at a storage node serving as one electrode and has the other electrode connected to a cell plate CP, an access transistor 722 activated by word line WL0 to electrically connect the storage node of capacitor 724 and bit line BLL0, a capacitor 726 which stores data at a storage node serving as one electrode and has the other electrode connected to a cell plate CP, and an access transistor 728 activated by word line WLn-1 to electrically connect the storage node of capacitor 726 and bit line /BLL0.
Memory cell array 644 further includes a capacitor 764 which stores data at a storage node serving as one electrode and has the other electrode connected to a cell plate CP, an access transistor 762 activated by word line WL0 to electrically connect the storage node of capacitor 764 and bit line BLL1, a capacitor 766 which stores data at a storage node serving as one electrode and has the other electrode connected to a cell plate CP, and an access transistor 768 activated by word line WLn-1 to electrically connect the storage node of capacitor 766 and bit line /BLL1.
Although not shown, word lines WL1 to WLn-2 are similarly connected to capacitors and access transistors.
Memory cell array 648 includes a capacitor 754 which stores data at a storage node serving as one electrode and has the other electrode connected to a cell plate CP, an access transistor 752 activated by word line WLn to electrically connect the storage node of capacitor 754 and bit line BLR0, a capacitor 756 which stores data at a storage node serving as one electrode and has the other electrode connected to a cell plate CP, and an access transistor 758 activated by word line WL2n-1 to electrically connect the storage node of capacitor 756 and bit line /BLR0.
Memory cell array 648 further includes a capacitor 794 which stores data at a storage node serving as one electrode and has the other electrode connected to a cell plate CP, an access transistor 792 activated by word line WLn to electrically connect the storage node of capacitor 794 and bit line /BLR1, a capacitor 796 which stores data at a storage node serving as one electrode and has the other electrode connected to a cell plate CP, and an access transistor 798 activated by word line WL2n-1 to electrically connect the storage node of capacitor 796 and bit line /BLR1.
Although not shown, word lines WLn+1 to WL2n-1 are similarly connected to capacitors and access transistors.
I/O gate-sense amplifier 646 includes a bit line isolation gate 730 activated by bit line isolation control signal BLIL to connect bit lines BLL0 and BL0, a bit line isolation gate 732 activated by bit line isolation control signal BLIL to connect bit lines /BLL0 and /BL0, a bit line isolation gate 742 activated by a bit line isolation control signal BLIR to connect bit lines BLR0 and BL0, a bit line isolation gate 744 activated by bit line isolation control signal BLIR to connect bit lines /BLR0 and /BL0, and a sense amplifier 734 activated in a prescribed timing to amplify the potential difference between bit lines BL0 and /BL0.
Hereinafter, I/O lines provided corresponding to bit lines BL0, /BL0, BL1 and /BL1 are called I/O lines IOA, /IOA, IOB, and /IOB, respectively.
I/O gate-sense amplifier 646 further includes an I/O line isolation gate 736 activated by column selecting line CSL0 to connect bit lines BL0 and I/O line IOA, an I/O line isolation gate 738 activated by column selecting line CSL0 to connect bit line BL0 to connect bit lines /BL0 and /IOA, and an equalizer 740 activated in a prescribed timing to connect bit lines BL0 and /BL0 to attain a prescribed potential.
I/O gate-sense amplifier 646 further includes a bit line isolation gate 770 activated by bit line isolation control signal BLIL to connect bit lines BLL1 and BL1, a bit line isolation gate 772 activated by bit line isolation control signal BLIL to connect bit lines /BLL1 and /BL1, a bit line isolation gate 782 activated by bit line isolation control signal BLIR to connect bit lines BLR1 and BL1, a bit line isolation gate 784 activated by bit line isolation control signal BLIR to connect bit lines /BLR1 and /BL1, a sense amplifier 774 activated in a prescribed timing to amplify the potential difference between bit lines BL1 and /BL1, an I/O isolation gate 776 activated by column selecting line CSL0 to connect bit line BLR1 and I/O line IOB, an I/O line isolation gate 778 activated by column selecting line CSL0 to connect bit line BLR1 and I/O line /IOB, and an equalizer 780 activated in a prescribed timing to connect bit lines BL1 and BLL1 to attain a prescribed potential.
FIG. 17 shows the portion corresponding to column selecting line CSL0 in detail, and portions corresponding to column selecting lines CSL1 to CSL7 have the same configuration.
In FIG. 17, two pairs of I/O lines are placed in the central part of I/O gate-sense amplifier 646 in the order of IOA, /IOB, /IOA and IOB.
FIG. 18 is a schematic diagram of the arrangement of I/O lines and bit lines shown in FIG. 17.
Referring to FIG. 18, the connecting portion between the I/O line and the bit line is formed inside a square 811 having sides 811a, 811b, 811c, and 811d.
Corners defined by sides 811a and 811b, 811b and 811c, 811c and 811d, and 811d and 811a correspond to corner portions 811f, 811g, 811h and 811e, respectively.
Transistors 830, 840, 842 and 836 are provided at corner portions 811h, 811e, 811f, and 811g, respectively, and at the central part of each of the transistors, a gate electrode 832 is provided in parallel to side 811a. Gate electrode 832 is for example composed of tungsten silicide.
Bit line BL0 is electrically connected to a first impurity region in transistor 830 at a contact portion 846. Bit line /BL0 is electrically connected to a first impurity region in transistor 836 at a contact portion 856. Bit line BL1 is electrically connected to a first impurity region in transistor 842 at a contact portion 858. Bit line /BL1 is electrically connected to a first impurity region in transistor 840 at contact portion 866.
Between sides 811d and 811b, I/O line IOA is provided along side 811d, and I/O line IOB is provided along side 811b. Between I/O lines IOA and IOB, I/O line /IOB parallel to I/O line IOA is provided adjacent to I/O line IOA, and between I/O lines /IOB and IOB, I/O line /IOA is provided parallel to I/O line IOB. These I/O lines are, for example, formed of a first aluminum layer.
I/O line IOA is electrically connected to a second impurity region in transistor 830 at a contact portion 840. I/O line /IOB is electrically connected to a second impurity region in transistor 840 at a contact portion 868. I/O line /IOA is connected to a second impurity region in transistor 836 at a contact portion 854. I/O line IOB is electrically connected to a second impurity region in transistor 842 at a contact portion 860.
An interconnection 834 is provided parallel to side 811a at the central part of square 811, and interconnection 834 is electrically connected to gate electrode 832 at contact portion 850.
In the middle between sides 811a and 811c, column selecting line CSL is provided parallel to side 811a. Column selecting line CSL is electrically connected to interconnection 834 at contact portion 852. Interconnection 834 is for example formed of the first aluminum layer, and column selecting line CSL is for example formed of a second aluminum layer.
Herein, in FIG. 18, I/O lines /IOB and /IOA are adjacent to each other. In general, parallel interconnections provided adjacent to each other in the same interconnection layer are highly likely to cause short circuit defects because of any condition fault occurring in etching in the manufacturing process. Let us assume now that, as represented by resistor 810 in FIG. 18, there is a short circuit defect between I/O lines /IOB and /IOA.
As can be seen from FIG. 16, when H level data is input from input terminal Din, data on I/O lines IOA, /IOB, /IOA and IOB attain H, L, L and H levels, respectively, and data on I/O lines /IOB and /IOA are the same data. As a result, if there is a short circuit fault between I/O lines IOB and /IOA, the state is observed as if the device is operating normally in a multi-bit test, even if one of the I/O lines is not connected to a memory cell, and therefore a separate I/O line short circuit fault test is necessary.